1. Field of Art
The disclosure generally relates to the field of electronic design automation (EDA), and more specifically to routing of power supply voltages for a standard cell that is used to design integrated circuits (ICs).
2. Description of the Related Art
Computer-aided cell-based design has been developed for quickly designing large scale ICs such as application specific integrated circuits (ASICs) and gate arrays. The cell is a circuit that has been pre-designed and pre-verified as a building block. Design technologies known as standard cell and gate array use different types of such building blocks. In a standard cell design, each distinct cell in a library may have unique geometries of active, gate, and metal levels. With gate arrays, however, each gate array cell shares the same building block, called a core cell that includes fixed active and gate level geometries. Different gate array cells are implemented using only metal interconnections between the active and gate elements of one or more core cells. Examples of a standard cell or gate array cell include an inverter, a NAND gate, a NOR gate, a flip flop, and other similar logic circuits.
During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design. The library includes cells that have been designed for a given integrated circuit (IC) manufacturing process, such as complementary metal oxide semiconductor (CMOS) fabrication. The cells generally have a fixed height but a variable width, which enables the cells to be placed in rows. Cells do not change from one design to the next, but the way in which they are interconnected will, to achieve the desired function in a given design. By being able to select the cells from the library for use in the design, the designer can quickly implement a desired functionality without having to custom design the entire integrated circuit from scratch. The designer will thus have a certain level of confidence that the integrated circuit will work as intended when manufactured without having to worry about the details of the individual transistors that make up each cell.
Because a designer will use many copies (called instances) of a cell in a particular design, it is important to optimize the cells to be as compact as possible. Otherwise, any inefficiency will be replicated with every instance of the standard cell in the design. Advantages of smaller cells include being able to fit complex circuits within a limited amount of space. Having smaller cells also reduces the physical size of an integrated circuit, thereby reducing the cost of manufacturing the integrated circuit.
It also important for cells to be designed so that routing connections can be made efficiently. Routing in an IC design is accomplished through routing elements, such as traces in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias connect one metal layer to another. These routing elements perform at least two functions: they connect individual transistors that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit. For example, clock signals, reset signals, test signals, and supply voltages may be carried through these routing elements. A properly designed cell minimizes congestion in routing global interconnections, which reduces the number of metal layers that need to be used in manufacturing the integrated circuit.
Another concern is complying with various design rules. Restrictive design rules are new design rules governing layouts of objects (such as metal, polysilicon, and vias) which are more restrictive in nature than those imposed in older semiconductor processes. Some restrictive design rules account for inevitable variations during the manufacturing of an integrated circuit and are needed by the foundry to manufacture a chip. Examples of restrictive design rules include requiring all gates in the layout to have the same pitch (i.e., be spaced at equal distances) or requiring all gates in the layout to be in the same direction. An example of a normal rule is a rule that that metal wires must have a minimum spacing to other metal wires within the same layer. Other design rules reflect best practices that enable efficient chip routing, but are not absolute rules needed by the foundry to manufacture a chip. For example, it is preferred that traces within some metal layers all run in the same direction to reduce chip level routing congestion.